View LPC2104BBD48_236704.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM
Rev. 04 -- 05 February 2004 Product data
1. General description
The LPC2104, 2105 and 2106 are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128 kbytes (kB) of embedded high speed flash memory. A 128 bit wide memory interface and a unique accelerator architecture enable 32 bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty. Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM options up to 64 kilobytes, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32 bit timers, PWM channels and 32 GPIO lines make these microcontrollers particularly suitable for industrial control and medical systems.
2. Features
2.1 Key features
s 16/32 bit ARM7TDMI-S processor. s 16/32/64 kB on-chip Static RAM. s 128 kB on-chip Flash Program Memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation. s In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms. s Vectored Interrupt Controller with configurable priorities and vector addresses. s EmbeddedICE-RT interface enables breakpoints and watchpoints. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software. s Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution. s Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s) and SPI. s Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog. s Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 x 7 mm2) package.
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
s 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop. s On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. s Two low power modes, Idle and Power-down. s Processor wake-up from Power-down mode via external interrupt. s Individual enable/disable of peripheral functions for power optimization. s Dual power supply: x CPU operating voltage range of 1.65 V to 1.95 V (1.8 V 8.3%). x I/O power supply range of 3.0 V to 3.6 V (3.3 V 10%) with 5 V tolerant I/O pads.
3. Ordering information
Table 1: Ordering information Package Name LPC2104BBD48 LPC2105BBD48 LPC2106BBD48 LPC2106FHN48 LQFP48 LQFP48 LQFP48 Description Version plastic low profile quad flat package, 48 leads, SOT313-2 body 7 x 7 x 1.4 mm plastic low profile quad flat package, 48 leads, SOT313-2 body 7 x 7 x 1.4 mm plastic low profile quad flat package, 48 leads, SOT313-2 body 7 x 7 x 1.4 mm SOT619-1 Type number
HVQFN48 plastic thermal enhanced very thin quad flat package, no leads, 48 terminals, body 7 x 7 x 0.85
3.1 Ordering options
Table 2: Part options Flash memory 128 kB 128 kB 128 kB 128 kB RAM 16 kB 32 kB 64 kB 60 kB Temperature range 0 to +70, LQFP 0 to +70, LQFP 0 to +70, LQFP -40 to +85, HVQFN Type number LPC2104BBD48 LPC2105BBD48 LPC2106BBD48 LPC2106FHN48
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
2 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4. Block diagram
TRST(1) TMS(1) TCK(1) TDI(1) TDO(1)
RTCK
XTAL1 PLL system clock
XTAL2
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
SYSTEM FUNCTIONS
ARM7TDMI-S
AHB BRIDGE ARM7 LOCAL BUS
VECTORED INTERRUPT CONTROLLER
AMBA AHB (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER AHB TO VPB VPB BRIDGE DIVIDER
AHB DECODER
16/32/64 kB SRAM
128 kB FLASH
APB(2) EINT0* EINT1* EINT2* EXTERNAL INTERRUPTS I2C SERIAL INTERFACE SCL* SDA*
CAP0..2* MAT0..2*
CAPTURE/ COMPARE TIMER 0
SPI SERIAL INTERFACE
CAP0..3* MAT0..3*
CAPTURE/ COMPARE TIMER 1
UART0
GPIO (32 PINS)
GENERAL PURPOSE I/O
UART1
MODEM CONTROL (6 PINS)*
PWM1..6*
PWM0
WATCHDOG TIMER
REAL TIME CLOCK
SYSTEM CONTROL
*Shared with GPIO
(1) When test/debug interface is used, GPIO/other function sharing these pins are not available. (2) APB with Ready signal.
Fig 1. Block diagram.
9397 750 12792 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
RST VDD VSS SCK* MOSI* MISO* SSEL* TxD* RxD* TxD* RxD*
002aaa412
3 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5. Pinning information
5.1 Pinning
46 P0.16/EINT0/MAT0.2
handbook, full pagewidth
P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO NC VDD1.8 (CORE) RST VSS1 P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS
1 2 3 4 5 6
37 P0.12/DSR1/MAT1.0
41 P0.13/DTR1/MAT1.1
47 P0.17/CAP1.2/TRST
39 P0.26/TRACESYNC
48 P0.18/CAP1.3/TMS
44 P0.14/DCD1/EINT1
38 P0.25/PIPESTAT2
45 P0.15/RI1/EINT2
40 VDD3-1 (I/O)
43 VSS4
42 NC
36 P0.11/CTS1/CAP1.1 35 P0.10/RTS1/CAP1.0 34 P0.24/PIPESTAT1 33 P0.23/PIPESTAT0 32 P0.22/TRACECLK 31 VSS3 30 P0.9/RxD1/PWM6 29 P0.8/TxD1/PWM4 28 P0.7/SSEL/PWM2 27 DBGSEL 26 RTCK 25 NC
LPC2104/2105/2106
7 8 9
P0.29/TRACEPKT2/TCK 10 X1 11 X2 12
P0.0/TxD0/PWM1 13
P0.1/RxD0/PWM3 14
P0.30/TRACEPKT3/TDI 15
P0.31/EXTIN0/TDO 16
VDD3-2 (I/O) 17
P0.2/SCL/CAP0.0 18
VSS2 19
NC 20
P0.3/SDA/MAT0.0 21
P0.4/SCK/CAP0.1 22
P0.5/MISO/MAT0.1 23
P0.6/MOSI/CAP0.2 24
002aaa411
Fig 2. Pinning.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
4 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5.2 Pin description
Table 3: Symbol P0.0 to P0.31 Pin description Pin Type Description Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. 13, 14, 18, I/O 21-24, 28-30, 35-37, 41, 44-48, 1-3, 32-34, 38, 39, 8-10, 15, 16 13 I/O O O 14 I/O I O 18 I/O I/O I 21 I/O I/O O 22 I/O I/O I 23 I/O I/O O 24 I/O I/O I 28 I/O I O 29 I/O O O
P0.0 -- Port 0 bit 0. TxD0 -- Transmitter output for UART 0. PWM1 -- Pulse Width Modulator output 1. P0.1 -- Port 0 bit 1. RxD0 -- Receiver input for UART 0. PWM3 -- Pulse Width Modulator output 3. P0.2 -- Port 0 bit 2. SCL -- I2C clock input/output. Open drain output (for I2C compliance). CAP0.0 -- Capture input for Timer 0, channel 0. P0.3 -- Port 0 bit 3. SDA -- I2C data input/output. Open drain output (for I2C compliance). MAT0.0 -- Match output for Timer 0, channel 0. P0.4 -- Port 0 bit 4. SCK -- Serial clock. SPI clock output from master or input to slave. CAP0.1 -- Capture input for Timer 0, channel 1. P0.5 -- Port 0 bit 5. MISO -- Master In Slave Out. Data input to SPI master or data output from SPI slave. MAT0.1 -- Match output for Timer 0, channel 1. P0.6 -- Port 0 bit 6. MOSI -- Master Out Slave In. Data output from SPI master or data input to SPI slave. CAP0.2 -- Capture input for Timer 0, channel 2. P0.7 -- Port 0 bit 7. SSEL -- Slave Select. Selects the SPI interface as a slave. PWM2 -- Pulse Width Modulator output 2. P0.8 -- Port 0 bit 8. TxD1 -- Transmitter output for UART 1. PWM4 -- Pulse Width Modulator output 4.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
5 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table 3: Symbol
Pin description...continued Pin 30 Type I/O I O 35 I/O O I 36 I/O I I 37 I/O I O 41 I/O O O 44 I/O I I 45 I/O I O 46 I/O I O 47 I/O I I 48 I/O I I 1 I/O O I 2 I/O O I 3 I/O O O 32 I/O O Description P0.9 -- Port 0 bit 9. RxD1 -- Receiver input for UART 1. PWM6 -- Pulse Width Modulator output 6. P0.10 -- Port 0 bit 10. RTS1 -- Request to Send output for UART 1. CAP1.0 -- Capture input for Timer 1, channel 0. P0.11 -- Port 0 bit 11. CTS1 -- Clear to Send input for UART 1. CAP1.1 -- Capture input for Timer 1, channel 1. P0.12 -- Port 0 bit 12. DSR1 -- Data Set Ready input for UART 1. MAT1.0 -- Match output for Timer 1, channel 0. P0.13 -- Port 0 bit 13. DTR1 -- Data Terminal Ready output for UART 1. MAT1.1 -- Match output for Timer 1, channel 1. P0.14 -- Port 0 bit 14. DCD1 -- Data Carrier Detect input for UART 1. EINT1 -- External interrupt 1 input. P0.15 -- Port 0 bit 15. RI1 -- Ring Indicator input for UART 1. EINT2 -- External interrupt 2 input. P0.16 -- Port 0 bit 16. EINT0 -- External interrupt 0 input. MAT0.2 -- Match output for Timer 0, channel 2. P0.17 -- Port 0 bit 17. CAP1.2 -- Capture input for Timer 1, channel 2. TRST -- Test Reset for JTAG interface, primary JTAG pin group. P0.18 -- Port 0 bit 18. CAP1.3 -- Capture input for Timer 1, channel 3. TMS -- Test Mode Select for JTAG interface, primary JTAG pin group. P0.19 -- Port 0 bit 19. MAT1.2 -- Match output for Timer 1, channel 2. TCK -- Test Clock for JTAG interface, primary JTAG pin group. P0.20 -- Port 0 bit 20. MAT1.3 -- Match output for Timer 1, channel 3. TDI -- Test Data In for JTAG interface, primary JTAG pin group P0.21 -- Port 0 bit 21. PWM5 -- Pulse Width Modulator output 5. TDO -- Test Data Out for JTAG interface, primary JTAG pin group. P0.22 -- Port 0 bit 22. TRACECLK -- Trace Clock. Standard I/O port with internal pull-up.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12792
Product data
Rev. 04 -- 05 February 2004
6 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table 3: Symbol
Pin description...continued Pin 33 34 38 39 Type I/O O I/O O I/O O I/O O 8 I/O O I 9 I/O O I 10 I/O O I 15 I/O O I 16 I/O I O Description P0.23 -- Port 0 bit 23. PIPESTAT0 -- Pipeline Status, bit 0. Standard I/O port with internal pull-up. P0.24 -- Port 0 bit 24. PIPESTAT1 -- Pipeline Status, bit 1. Standard I/O port with internal pull-up. P0.25 -- Port 0 bit 25. PIPESTAT2 -- Pipeline Status, bit 2. Standard I/O port with internal pull-up. P0.26 -- Port 0 bit 26. TRACESYNC -- Trace Synchronization Standard I/O port with internal pull-up. P0.27 -- Port 0 bit 27. TRACEPKT0 -- Trace Packet, bit 0. Standard I/O port with internal pull-up. TRST -- Test Reset for JTAG interface, secondary JTAG pin group. P0.28 -- Port 0 bit 28. TRACEPKT1 -- Trace Packet, bit 1. Standard I/O port with internal pull-up. TMS -- Test Mode Select for JTAG interface, secondary JTAG pin group P0.29 -- Port 0 bit 29. TRACEPKT2 -- Trace Packet, bit 2. Standard I/O port with internal pull-up. TCK -- Test Clock for JTAG interface, secondary JTAG pin group. P0.30 -- Port 0 bit 30. TRACEPKT3 -- Trace Packet, bit 3. Standard I/O port with internal pull-up. TDI -- Test Data In for JTAG interface, secondary JTAG pin group. P0.31 -- Port 0 bit 31. EXTIN0 -- External Trigger Input. Standard I/O port with internal pull-up. TDO -- Test Data out for JTAG interface, secondary JTAG pin group. Returned Test Clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Also used during debug mode entry to select primary or secondary JTAG pins with the 48-pin package. Bi-directional pin with internal pull-up. Debug Select: When LOW, the part operates normally. When HIGH, debug mode is entered. Input pin with internal pull-down. External Reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Ground: 0 V reference. 1.8 V Core Power Supply: This is the power supply voltage for internal circuitry. 3.3 V Pad Power Supply: This is the power supply voltage for the I/O ports. Not Connected: These pins are not connected in the 48 pin package.
RTCK
26
I/O
DBGSEL RST
27 6
I I
X1 X2 VSS1 - VSS4 VDD1.8 VDD3 NC
11 12 7, 19, 31, 43 5 17, 40 4, 20, 25, 42
I O I I I -
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
7 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
* The standard 32-bit ARM set. * A 16-bit THUMB set.
The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-Chip Flash program memory
The LPC2104, LPC2105 and LPC2106 incorporate a 128 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is used, 120 kB of Flash memory is available for user code.
6.3 On-Chip static RAM
On-Chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2104 provides a 16 kB static RAM, the LPC2105 provides a 32 kB static RAM, and the LPC2106 provides a 64 kB static RAM.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
8 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.4 Memory map
The LPC2104, LPC2105 and LPC2106 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory (the default) or on-chip static RAM. This is described in Section 6.17 "System control".
4.0 GB AHB PERIPHERALS 3.75 GB VPB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 3FFF 16 KBYTE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF 128 KBYTE ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000
002aaa415
Fig 3. LPC2104 memory map.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
9 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4.0 GB AHB PERIPHERALS 3.75 GB VPB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF 32 KBYTE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF 128 KBYTE ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000
002aaa414
Fig 4. LPC2105 memory map.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
10 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4.0 GB AHB PERIPHERALS 3.75 GB VPB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF 64 KBYTE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF 128 KBYTE ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000
002aaa413
Fig 5. LPC2106 memory map.
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
11 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.5.1 Interrupt sources Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Table 4: Block WDT ARM Core ARM Core Timer 0 Timer 1 UART 0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) UART 1 Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 I2C SPI PLL RTC Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) SI (state change) SPIF, MODF reserved PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) 8 9 10 11 12 13 7 6 5 VIC channel # 0 1 2 3 4
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
12 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Interrupt sources...continued Flag(s) VIC channel # 14 15 16
Table 4: Block
System Control External Interrupt 0 (EINT0) System Control External Interrupt 1 (EINT1) System Control External Interrupt 2 (EINT2)
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module contains two registers as shown in Table 5.
Table 5: Address 0xE002C000 0xE002C004 Name PINSEL0 PINSEL1 Description Pin function select register 0 Pin function select register 1 Access Read/Write Read/Write
6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in Table 6. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Settings other than those shown in Table 6 are reserved, and should not be used
Table 6: PINSEL0 1:0 Pin function select register 0 (PINSEL0 - 0xE002C000) Pin name P0.0 Value 0 0 1 3:2 P0.1 0 0 1 5:4 P0.2 0 0 1 7:6 P0.3 0 0 1 9:8 P0.4 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Function GPIO Port 0.0 TxD (UART 0) PWM1 GPIO Port 0.1 RxD (UART 0) PWM3 GPIO Port 0.2 SCL (I2C) 0 Capture 0.0 (Timer 0) GPIO Port 0.3 SDA (I2C) 0 Match 0.0 (Timer 0) GPIO Port 0.4 SCK (SPI) Capture 0.1 (Timer 0) 0 0 Value after Reset 0
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
13 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Pin function select register 0 (PINSEL0 - 0xE002C000)...continued Pin name P0.5 Value 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Function GPIO Port 0.5 MISO (SPI) Match 0.1 (Timer 0) GPIO Port 0.6 MOSI (SPI) Capture 0.2 (Timer 0) GPIO Port 0.7 SSEL (SPI) PWM2 GPIO Port 0.8 TxD UART 1 PWM4 GPIO Port 0.9 RxD (UART 1) PWM6 GPIO Port 0.10 RTS (UART1) Capture 1.0 (Timer 1) GPIO Port 0.11 CTS (UART1) Capture 1.1 (Timer 1) GPIO Port 0.12 DSR (UART1) Match 1.0 (Timer 1) GPIO Port 0.13 DTR (UART 1) Match 1.1 (Timer 1) GPIO Port 0.14 CD (UART 1) EINT1 GPIO Port 0.15 RI (UART1) EINT2 0 0 0 0 0 0 0 0 0 0 Value after Reset 0
Table 6: PINSEL0 11:10
13:12
P0.6
0 0 1
15:14
P0.7
0 0 1
17:16
P0.8
0 0 1
19:18
P0.9
0 0 1
21:20
P0.10
0 0 1
23:22
P0.11
0 0 1
25:24
P0.12
0 0 1
27:26
P0.13
0 0 1
29:28
P0.14
0 0 1
31:30
P0.15
0 0 1
6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in Table 7. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Function control for the pins P0.17 - P0.31 is effective only when the DBGSEL input is pulled LOW during RESET.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
14 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Pin function select register 1 (PINSEL1 - 0xE002C004) Pin Name P0.16 Value 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 Function GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) GPIO Port 0.17 Capture 1.2 (Timer 1) GPIO Port 0.18 Capture 1.3 (Timer 1) GPIO Port 0.19 Match 1.2 (Timer 1) GPIO Port 0.20 Match 1.3 (Timer 1) GPIO Port 0.21 PWM5 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 TRST GPIO Port 0.28 TMS GPIO Port 0.29 TCK GPIO Port 0.30 TDI GPIO Port 0.31 TDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after Reset 0
Table 7: PINSEL1 1:0
3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30
P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 P0.28 P0.29 P0.30 P0.31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.9 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. 6.9.1 Features
* Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset.
9397 750 12792 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
15 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.10 UARTs
The LPC2104, LPC2105 and LPC2106 each contain two UARTs. One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines. 6.10.1 Features
* * * * *
16 byte Receive and Transmit FIFOs. Register locations conform to `550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes Built-in baud rate generator. Standard modem interface signals included on UART 1.
6.11 I2C serial I/O controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be controlled by more than one bus master connected to it. I2C implemented in LPC2104, LPC2105 and LPC2106 supports bit rate up to 400 kbit/s (Fast I2C). 6.11.1 Features
* Standard I2C compliant bus interface. * Easy to configure as Master, Slave, or Master/Slave. * Programmable clocks allow versatile rate control. * Bidirectional data transfer between masters and slaves. * Multi-master bus (no central master). * Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
* Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
* Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
* The I2C bus may be used for test and diagnostic purposes.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
16 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.12 SPI serial I/O controller
The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.12.1 Features
* Compliant with Serial Peripheral Interface (SPI) specification. * Synchronous, Serial, Full Duplex, Communication. * Combined SPI master and slave. * Maximum data bit rate of one eighth of the input clock rate. 6.13 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 6.13.1 Features
* A 32-bit Timer/Counter with a programmable 32-bit Prescaler. * Up to four (TImer 1) and three (Timer 0) 32-bit capture channels, that can take a
snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
* Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match
registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
6.14 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to `feed' (or reload) the Watchdog within a predetermined amount of time.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
17 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.14.1
Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
* Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. * Flag to indicate Watchdog reset. * Programmable 32-bit timer with internal pre-scaler. * Selectable time period from (tpclk x 256 x 4) to (tpclk x 232 x 4) in multiples of
tpclk x 4.
6.15 Real time clock
The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.15.1 Features
* Measures the passage of time to maintain a calendar and clock. * Ultra Low Power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
* Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
6.16 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2104, LPC2105 and LPC2106. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single
9397 750 12792 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
18 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.16.1 Features
* Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
* The match registers also allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Supports single edge controlled and/or double edge controlled PWM outputs.
Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
* Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
* Double edge controlled PWM outputs can be programmed to be either positive
going or negative going pulses.
* Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must "release" new match values before they can become effective.
* May be used as a standard timer if the PWM mode is not enabled. * A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
19 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.17 System control
6.17.1 Crystal oscillator The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output frequency is called FOSC and the ARM processor clock frequency is referred to as cclk for purposes of rate equations, etc. FOSC and cclk are the same value unless the PLL is running and connected. Refer to Section 6.17.2 "PLL" for additional information. 6.17.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle.The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. 6.17.3 Reset and wake-up timer Reset has two sources on the LPC2104, LPC2105 and LPC2106: the RST pin and Watchdog Reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip Flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
20 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.17.4
External interrupt inputs The LPC2104, LPC2105 and LPC2106 include three External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
6.17.5
Memory Mapping Control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip Flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
6.17.6
Power Control The LPC2104, LPC2105 and LPC2106 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
6.17.7
VPB bus The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes. The first is that the VPB bus cannot operate at the highest speeds of the CPU. In order to compensate for this, the VPB bus may be slowed down to one half or one fourth of the processor clock rate. The default condition at reset is for the VPB bus to run at one quarter of the CPU clock. The second purpose of the VPB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the VPB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.18 Emulation and debugging
The LPC2104, LPC2105 and LPC2106 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Each of these functions requires a trade-off of debugging features versus device pins. Because the LPC2104, LPC2105 and LPC2106 are provided in a small package, there is no room for permanently assigned JTAG or Trace pins. An alternate JTAG port allows an option to debug functions assigned to the pins used by the primary JTAG port.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
21 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.18.1
Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function in-built. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic.
6.18.2
Embedded trace Since the LPC2104, LPC2105 and LPC2106 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.
6.18.3
RealMonitorTM RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2104, LPC2105 and LPC2106 contain a specific configuration of RealMonitor software programmed into the on-chip Flash memory.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
22 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
7. Limiting values
Table 8: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD1.8 VDD3 Vi Vi I I Tstg P Supply voltage, internal rail Supply voltage, external rail DC input voltage, 5 V tolerant I/O pins[3][4] DC input voltage, other I/O pins[2][3] DC supply current per supply pin[5] DC ground current per ground Storage temperature[6] Power dissipation (based on package heat transfer, not device power consumption) pin[5] Conditions Min -0.5 -0.5 -0.5 -0.5 -40 1.5 Max +2.5 +3.6 6.0 VDD3 + 0.5 100 100 125 Unit V V V V mA mA C W
[1]
[2] [3] [4] [5] [6]
The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Section 8 "Static characteristics" and Section 9 "Dynamic characteristics" of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Not to exceed 4.6 V. Including voltage on outputs in 3-state mode. Only valid when the VDD3 supply voltage is present. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
23 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
8. Static characteristics
Table 9: Static characteristics Tamb = 0 C to +70 C for commercial, unless otherwise specified. Symbol Parameter VDD1.8 VDD3 IIL IIH IOZ Ilatchup Vi Vo VIH VIL Vhys VOH VOL IOH IOL IOH IOL IPD IPU IDD1.8 Supply voltage External rail supply voltage LOW level input current, no pull-up HIGH level input current, no pull down 3-state output leakage, no pull-up/down I/O latch-up current Input voltage[3][4][5] Vi = 0 Vi = VDD3 Vo = 0, Vo = VDD3 -(0.5 VDD3) < V < (1.5 VDD3) Tj < 125 C 0 0 2.0 IOH = -4 mA IOL = -4 mA VOH = VDD3 - 0.4 V VOL = 0.4 V VOH = 0 VOL = VDD3 VDD3 - 0.4 -4 4 20 -25 V[8] 0 0.4 50 -50 0 30 5.5 VDD3 0.8 0.4 -45 50 100 -65 0 V V V V V V V mA mA mA mA A A A mA Output voltage, output active HIGH level input voltage LOW level input voltage Hysteresis voltage HIGH level output voltage[6] LOW level output voltage[6] HIGH level output LOW level output current[6] current[6] Conditions Min 1.65 3.0 100 Typ[1] 1.8 3.3 Max 1.95 3.6 3 3 3 Unit V V A A A mA
Standard Port pins, RST, RTCK, and DBGSEL
HIGH level short circuit current[7] LOW level short circuit current[7]
Pull-down current (applies to Vi = 5 V[8] DBGSEL) Pull-up current (applies to P0.22 - P0.31) Active Mode Vi = 0 VDD3 < Vi< 5 VDD1.8 = 1.8 V, cclk = 60 MHz, Tamb = 25 C, code while(1){} executed from FLASH, no active peripherals Power-down Mode VDD1.8 = 1.8 V, Tamb = +25 C, VDD1.8 = 1.8 V, Tamb = +85 C
0.7 VTOL -
10 50 0.5 VTOL -
500 0.3 VTOL 0.4
A A V V V V
I2C VIH VIL
pins HIGH level input voltage LOW level input voltage Hysteresis voltage LOW level output voltage[6] VTOL is from 4.5 V to 5.5 V VTOL is from 4.5 V to 5.5 V VTOL is from 4.5 V to 5.5 V IOL = 3 mA
Vhys VOL
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
24 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table 9: Static characteristics...continued Tamb = 0 C to +70 C for commercial, unless otherwise specified. Symbol Parameter Ilkg Input leakage to VSS Conditions Vi = VDD3 Vi = 5 V Oscillator pins X1 input Voltages X2 output Voltages
[1] [2] [3] [4] [5] [6] [7] [8]
Min 0 0
Typ[1] 2 10 -
Max 4 22 VDD1.8 VDD1.8
Unit A A
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Pin capacitance is characterized but not tested. Including voltage on outputs in 3-state mode. VDD3 supply voltages must be present. 3-state outputs go into 3-state mode when VDD3 is grounded. Accounts for 100 mV voltage drop in all supply lines. Only allowed for a short time period. Minimum condition for Vi = 4.5 V, maximum condition for Vi = 5.5 V.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
25 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
9. Dynamic characteristics
Table 10: Characteristics Tamb = 0 C to +70 C for commercial, -40 C to +85 C for industrial, VDD1.8, VDD3 over specified ranges[1] Symbol External Clock fosc Oscillator frequency supplied by an external oscillator (signal generator) External clock frequency supplied by an external crystal oscillator External clock frequency if on-chip PLL is used External clock frequency if ISP is used for initial code download tC tCHCX tCLCX tCLCH tCHCL Port Pins tRISE tFALL I2C pins tf Output fall time from VIH to VIL 20 + 0.1 x Cb[2] ns Port output rise time (except P0.2, P0.3) Port output fall time (except P0.2, P0.3) ns ns External oscillator clock period Clock HIGH time Clock LOW time Clock rise time Clock fall time 1 1 10 10 20 tc x 0.4 tc x 0.4 50 30 25 25 1000 5 5 MHz MHz MHz MHz ns ns ns ns ns Parameter Conditions Min Typ[1] Max Unit
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Bus capacitance Cb in pF, from 10 pF to 400 pF.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
26 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
9.1 Timing
VDD - 0.5 V 0.45 V
0.2 VDD + 0.9 0.2 VDD - 0.1 V tCHCX
tCHCL
tCLCX
tC
tCLCH
002aaa416
Fig 6. External clock timing.
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
27 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
10. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 7. SOT313-2
9397 750 12792 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
28 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A1 c
detail X
e1 e 13 L 12 25 e
1/2
C e b 24 vMCAB wMC y1 C y
Eh
1/2
e2 e
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 8. SOT619-1
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
29 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
11. Revision history
Table 11: Rev Date 04 20040205 Revision history CPCN Description Product data (9397 750 12792); 853-2425 ECN 01-A15458f of 28 January 2004 Modifications:
* * * *
03 02 01 20031007 20030611 20030425 -
Table 4 "Interrupt sources" on page 12; removed line in PWM. Table 10 "Characteristics" on page 26; adjusted values for fOSC and tC. Added HVQFN48 package. On-chip crystal oscillator operating range changed from "10 MHz to 25 MHz" to "1 MHz to 30 MHz"
Product data (9397 750 12142); ECN 853-2425 30389 of 30 September 2003 Product data (9397 750 11499); ECN 853-2425 29919 of 09 May 2003 Product data (9397 750 11414); ECN 853-2425 29855 of 22 April 2003
9397 750 12792
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
30 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
12. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
13. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
15. Licenses
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
14. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
16. Trademarks
RealMonitor -- is a trademark of ARM, Inc.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 12792
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 -- 05 February 2004
31 of 32
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Contents
1 2 2.1 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.8 6.9 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.17.2 6.17.3 6.17.4 6.17.5 6.17.6 6.17.7 6.18 6.18.1 6.18.2 6.18.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Architectural overview. . . . . . . . . . . . . . . . . . . . 8 On-Chip Flash program memory . . . . . . . . . . . 8 On-Chip static RAM . . . . . . . . . . . . . . . . . . . . . 8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 11 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13 Pin function select register 0 (PINSEL0 - 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . 13 Pin function select register 1 (PINSEL1 - 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . 14 General purpose parallel I/O. . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C serial I/O controller . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General purpose timers . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pulse width modulator . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System control . . . . . . . . . . . . . . . . . . . . . . . . 20 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 20 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reset and wake-up timer . . . . . . . . . . . . . . . . 20 External interrupt inputs . . . . . . . . . . . . . . . . . 21 Memory Mapping Control . . . . . . . . . . . . . . . . 21 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . 21 VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Emulation and debugging . . . . . . . . . . . . . . . . 21 Embedded ICE . . . . . . . . . . . . . . . . . . . . . . . . 22 Embedded trace . . . . . . . . . . . . . . . . . . . . . . . 22 RealMonitorTM. . . . . . . . . . . . . . . . . . . . . . . . . 22 7 8 9 9.1 10 11 12 13 14 15 16 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 26 27 28 30 31 31 31 31 31
(c) Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 05 February 2004 Document order number: 9397 750 12792

▲Up To Search▲

Price & Availability of LPC2104BBD48

	To Download LPC2104BBD48 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .